Etude des transistors MOSFET à barrière Schottky, à canal Silicium et Germanium sur couches minces

Until the early 2000’s Dennard’s scaling rules at the transistor level have enabled to achieve a performance gain while still preserving the basic structure of the MOSFET building block from one generation to the next. However, this conservative approach has already reached its limits as shown by the introduction of channel stressors for the sub-130 nm technological nodes, and later high-k/metal gate stacks for the sub-65 nm nodes. Despite the introduction of high-k gate dielectrics, constraints in terms of gate leakage and reliability have been delaying the diminution of the equivalent oxide thickness (EOT). Concurrently, lowering the supply voltage (VDD) has become a critical necessity to reduce both the active and passive power density in integrated circuits. Hence the challenge: how to keep decreasing both gate length and supply voltage faster than the EOT without losing in terms of ON-state/OFF-state performance trade-off? Several solutions can be proposed aiming at solving this conundrum for nanoscale transistors, with architectures in rupture with the plain old Silicon-based MOSFET with doped Source and Drain invented in 1960. One approach consists in achieving an ION increase while keeping IOFF (and Vth) mostly unchanged. Specifically, two options are considered in detail in this manuscript through a review of their respective historical motivations, state-of-the-art results as well as remaining fundamental (and technological) challenges: i/ the reduction of the extrinsic parasitic resistance through the implementation of metallic Source and Drain (Schottky Barrier FET architecture); ii/ the reduction of the intrinsic channel resistance through the implementation of Germanium-based mobility boosters (Ge CMOS, compressively-strained SiGe channels, n-sSi/p-sSiGe Dual Channel co-integration). In particular, we study the case of thin films on insulator (SOI, SiGeOI, GeOI substrates), a choice justified by: the preservation of the electrostatic integrity for the targeted sub-22nm nodes; the limitation of ambipolar leakage in SBFETs; the limitation of junction leakage in (low-bandgap) Ge-based FETs. Finally, we show why, and under which conditions the association of the SBFET architecture with a Ge-based channel could be potentially advantageous with respect to conventional Si CMOS.Jusqu’au début des années 2000, les règles de scaling de Dennard ont permis de réaliser des gains en performance tout en conservant la structure de la brique de base transistor d’une génération technologique à la suivante. Cependant, cette approche conservatrice a d’ores et déjà atteint ses limites, comme en témoigne l’introduction de la contrainte mécanique pour les générations sub-130nm, et les empilements de grille métal/high-k pour les nœuds sub-65nm. Malgré l’introduction de diélectriques à forte permittivité, des limites en termes de courants de fuite de grille et de fiabilité ont ralenti la diminution de l’épaisseur équivalente d’oxyde (EOT). De façon concommitante, la diminution de la tension d’alimentation (VDD) est devenue une priorité afin de réduire la densité de puissance dissipée dans les circuits intégrés. D’où le défi actuel: comment continuer de réduire à la fois la longueur de grille et la tension d’alimentation plus rapidement que l’EOT sans pour autant dégrader le rapport de performances aux états passant et bloqué (ON et OFF) ? Diverses solutions peuvent être proposées, passant par des architectures s’éloignant du MOSFET conventionnel à canal Si avec source et drain dopés tel que défini en 1960. Une approche consiste en réaliser une augmentation du courant passant (ION) tout en laissant le courant à l’état bloqué (IOFF) et la tension de seuil (Vth) inchangés. Concrètement, deux options sont considérées en détail dans ce manuscrit à travers une revue de leurs motivations historiques respectives, les résultats de l’état de l’art ainsi que les obstacles (fondamentaux et technologiques) à leur mise en œuvre : i/ la réduction de la résistance parasite extrinsèque par l’introduction de source et drain métalliques (architecture transistor à barrière Schottky) ; ii/ la réduction de la résistance de canal intrinsèque par l’introduction de matériaux à haute mobilité à base de Germanium (CMOS Ge, canaux SiGe en contrainte compressive, co-intégration Dual Channel n-sSi/p-sSiGe). En particulier, nous étudions le cas de couches minces sur isolant (substrats SOI, SiGeOI, GeOI), un choix motivé par: la préservation de l’intégrité électrostatique pour les nœuds technologiques sub-22nm; la limitation du courant de fuite ambipolaire dans les SBFETs; la limitation du courant de fuites de jonctions dans les MOSFETs à base de Ge (qui est un matériau à faible bandgap). Enfin, nous montrons pourquoi et dans quelles conditions l’association d’une architecture SBFET et d’un canal à base de Germanium peut être avantageuse vis-à-vis du CMOS Silicium conventionnel

Remote capacitive sensing in two-dimension quantum-dot arrays

We investigate gate-defined quantum dots in silicon on insulator nanowire field-effect transistors fabricated using a foundry-compatible fully-depleted silicon-on-insulator (FD-SOI) process. A series of split gates wrapped over the silicon nanowire naturally produces a $2\times n$ bilinear array of quantum dots along a single nanowire. We begin by studying the capacitive coupling of quantum dots within such a 2$\times$2 array, and then show how such couplings can be extended across two parallel silicon nanowires coupled together by shared, electrically isolated, 'floating' electrodes. With one quantum dot operating as a single-electron-box sensor, the floating gate serves to enhance the charge sensitivity range, enabling it to detect charge state transitions in a separate silicon nanowire. By comparing measurements from multiple devices we illustrate the impact of the floating gate by quantifying both the charge sensitivity decay as a function of dot-sensor separation and configuration within the dual-nanowire structure.Comment: 9 pages, 3 figures, 35 cites and supplementar

Single-electron control in a foundry-fabricated two-dimensional qubit array

Silicon spin qubits have achieved high-fidelity one- and two-qubit gates, above error correction thresholds, promising an industrial route to fault-tolerant quantum computation. A significant next step for the development of scalable multi-qubit processors is the operation of foundry-fabricated, extendable two-dimensional (2D) arrays. In gallium arsenide, 2D quantum-dot arrays recently allowed coherent spin operations and quantum simulations. In silicon, 2D arrays have been limited to transport measurements in the many-electron regime. Here, we operate a foundry-fabricated silicon 2x2 array in the few-electron regime, achieving single-electron occupation in each of the four gate-defined quantum dots, as well as reconfigurable single, double, and triple dots with tunable tunnel couplings. Pulsed-gate and gate-reflectometry techniques permit single-electron manipulation and single-shot charge readout, while the two-dimensionality allows the spatial exchange of electron pairs. The compact form factor of such arrays, whose foundry fabrication can be extended to larger 2xN arrays, along with the recent demonstration of coherent spin control and readout, paves the way for dense qubit arrays for quantum computation and simulation.Comment: 9 pages (including supplementary information and 5 figures

Pauli Blockade in a Few-Hole PMOS Double Quantum Dot limited by Spin-Orbit Interaction

We report on hole compact double quantum dots fabricated using conventional CMOS technology. We provide evidence of Pauli spin blockade in the few hole regime which is relevant to spin qubit implementations. A current dip is observed around zero magnetic field, in agreement with the expected behavior for the case of strong spin-orbit. We deduce an intradot spin relaxation rate $\approx$120\,kHz for the first holes, an important step towards a robust hole spin-orbit qubit

Reflectometry of charge transitions in a silicon quadruple dot

Gate-controlled silicon quantum devices are currently moving from academic proof-of-principle studies to industrial fabrication, while increasing their complexity from single- or double-dot devices to larger arrays. We perform gate-based high-frequency reflectometry measurements on a 2x2 array of silicon quantum dots fabricated entirely using 300 mm foundry processes. Utilizing the capacitive couplings within the dot array, it is sufficient to connect only one gate electrode to one reflectometry resonator and still establish single-electron occupation in each of the four dots and detect single-electron movements with high bandwidth. A global top-gate electrode adjusts the overall tunneling times, while linear combinations of side-gate voltages yield detailed charge stability diagrams. We support our findings with $\mathbf{k}\cdot\mathbf{p}$ modeling and electrostatic simulations based on a constant interaction model, and experimentally demonstrate single-shot detection of interdot charge transitions with unity signal-to-noise ratios at bandwidths exceeding 30 kHz. Our techniques may find use in the scaling of few-dot spin-qubit devices to large-scale quantum processors.Comment: 10 pages including appendices and 7 figure

Large dispersive interaction between a CMOS double quantum dot and microwave photons

We report a large coupling rate, $g_0/(2\pi)=183$ MHz, between the charge state of a double quantum dot in a CMOS split-gate silicon nanowire transistor and microwave photons in a lumped-element resonator formed by hybrid integration with a superconducting inductor. We enhance the coupling by exploiting the large interdot lever arm of an asymmetric split-gate device, $\alpha=0.72$, and by inductively coupling to the resonator to increase its impedance, $Z_\text{r}=560$ $\Omega$. In the dispersive regime, the large coupling strength at the DQD hybridisation point produces a frequency shift comparable to the resonator linewidth, the optimal setting for maximum state visibility. We exploit this regime to demonstrate rapid gate-based readout of the charge degree of freedom, with an SNR of 3.3 in 50 ns. In the resonant regime, the fast charge decoherence rate precludes reaching the strong coupling regime, but we show a clear route to spin-photon circuit quantum electrodynamics using hybrid CMOS systems.Comment: 9 pages, 7 figure

Integrating innovations:a qualitative analysis of referral non-completion among rapid diagnostic test-positive patients in Uganda's human African trypanosomiasis elimination programme

BACKGROUND: The recent development of rapid diagnostic tests (RDTs) for human African trypanosomiasis (HAT) enables elimination programmes to decentralise serological screening services to frontline health facilities. However, patients must still undertake multiple onwards referral steps to either be confirmed or discounted as cases. Accurate surveillance thus relies not only on the performance of diagnostic technologies but also on referral support structures and patient decisions. This study explored why some RDT-positive suspects failed to complete the diagnostic referral process in West Nile, Uganda. METHODS: Between August 2013 and June 2015, 85% (295/346) people who screened RDT-positive were examined by microscopy at least once; 10 cases were detected. We interviewed 20 RDT-positive suspects who had not completed referral (16 who had not presented for their first microscopy examination, and 4 who had not returned for a second to dismiss them as cases after receiving discordant [RDT-positive, but microscopy-negative results]). Interviews were analysed thematically to examine experiences of each step of the referral process. RESULTS: Poor provider communication about HAT RDT results helped explain non-completion of referrals in our sample. Most patients were unaware they were tested for HAT until receiving results, and some did not know they had screened positive. While HAT testing and treatment is free, anticipated costs for transportation and ancillary health services fees deterred many. Most expected a positive RDT result would lead to HAT treatment. RDT results that failed to provide a definitive diagnosis without further testing led some to question the expertise of health workers. For the four individuals who missed their second examination, complying with repeat referral requests was less attractive when no alternative diagnostic advice or treatment was given. CONCLUSIONS: An RDT-based surveillance strategy that relies on referral through all levels of the health system is inevitably subject to its limitations. In Uganda, a key structural weakness was poor provider communication about the possibility of discordant HAT test results, which is the most common outcome for serological RDT suspects in a HAT elimination programme. Patient misunderstanding of referral rationale risks harming trust in the whole system and should be addressed in elimination programmes